Some integrated semiconductor devices including a high power output field effect transistor (FET), a high frequency power FET or the like, include a plated heat sink (PHS) the PHS is formed on a back surface of a chip and connected to a source of the FET on the front surface of the chip through a via hole penetrating a substrate. The via hole reduces the source inductance of the FET and assists in radiation heat.
FIG. 4 is a cross-sectional view showing an example of such a semiconductor device. In FIG. 4, reference numeral 101a designates a semiconductor substrate. A source diffusion region 106 and a drain diffusion region 105 are formed on a surface of the substrate 101a. A source electrode layer 110 and a drain electrode layer 108 are arranged on the source diffusion region 106 and on the drain diffusion region 105, respectively. In addition, a gate electrode layer 109 is arranged on an active region formed between the source diffusion region 106 and the drain diffusion region 105. A via hole 101b penetrates the substrate 101a and the source electrode layer 110 is connected to a first Au layer 112 formed on the back surface of the substrate 101a by a second Au layer 111 formed by plating.
FIGS. 5(a) to 5(l) are cross-sectional views showing steps of forming a via hole in accordance with a conventional method for manufacturing a semiconductor device. In these figures, reference numeral 201a designates a semiconductor substrate and reference numeral 201b designates a via hole formed in the semiconductor substrate 201a. A first resist 202 is used as a mask in forming the via hole 201b. Reference numeral 203 designates a second resist. A first metal film 204 serves as a feeding layer at the time of plating. A third resist 205 is used as a mask in forming a second metal film 206 by electrolytic plating.
Next, the conventional method will be described in reference to the drawings. As shown in FIG. 5(a), the first resist 202 is applied on the semiconductor substrate 201a on which an element such as a transistor is formed. Then, as shown in FIG. 5(b), an opening is formed in the first resist 202 by photolithography at a position where the via hole is to be formed. Then, as shown in FIG. 5(c) , the via hole 201b is formed by dry etching. Thereafter, the first resist 202 is removed. Then, as shown in FIG. 5(d), the second resist 203 is applied to the entire surface. Thereafter, the second resist 203 is patterned as shown in FIG. 5(e) by usual photolithography. Then, as shown in FIG. 5(f), the metal film (Ti/Au laminated metal films or the like) 204 serving as the feeding layer is deposited on the entire surface by sputtering or the like. Then, as shown in FIG. 5(g), the third resist 205 serving as a mask at the time of plating is applied to the entire surface. Then, as shown in FIG. 5(h), a desired region of the third resist is removed by photolithography. Then as shown in FIG. 5(i), the metal film 206 is formed by electrolytic plating. Then, as shown in FIG. 5(j), the remaining third resist 205 is removed. Then, as shown in FIG. 5(k), the feeding layer 204 is removed using the metal film 206 as a mask. Then, the second resist 203 is removed. Thus, a structure shown in FIG. 5(l) can be obtained. In order to obtain the structure sown in FIG. 4, a bottom of the via hole 201a is exposed by grinding the back surface of the substrate 201a and then Au is plated onto the back surface of the substrate to form the PHS.
However, since the conventional method for manufacturing a semiconductor device is constituted as described above, it is necessary to pattern the resist after the via hole is formed. In this case, when the depth of the via hole is as deep as 30 to 100 microns, the resist is not evenly applied, so that the resist pattern can not be formed with high precision. In addition, since 20 microns or more of resist is applied in the via hole, the bottom of the via hole is not sufficiently exposed to light when a positive resist is used and the resist remains there. Therefore, it is necessary to use a negative resist as the plating mask. The negative resist has high absorptivity as compared with the positive resist and it swells during development. Therefore, its pattern precision is poor and its processing precision is not as high as that of the positive resist. In such a semiconductor device, when the metal film is formed in the via hole by plating, a plating pattern, such as wiring or another electrode, is formed at the same time, with the result that the process can be simplified in many cases. This plating uses pattern a mask pattern 2 to 3 microns wide. Therefore, the fact that the precision of the patterning of the resist is poor is a serious problem.